In a computing system with multiple processors, a typical method of inter-processor communication is via messages in a memory space accessible to both the sending and receiving processor. An example would be in a design of an I/O processor wherein the host processor desires to communicate with the I/O processor. The host processor writes instructions into a reserved area of memory accessible to both processors. The I/O processor realizes that the host processor has communicated to it by continuously polling the area in the memory reserved for host-I/O communications. If there are several programs running on the host processor that communicate with the I/O processor, there may be several reserved areas in the common memory that the I/O processor must poll. As the number of addresses that the I/O processor has to poll grows, the system performance will go down. This degradation is due to the I/O processor having to be granted ownership of the common memory bus every time it reads the memory. While the I/O processor owns the memory bus, the host processor must wait to access the common memory.
U.S. Pat. No. 5,404,489 issued Apr. 4, 1995 to Woods et al. for SYSTEM AND METHOD FOR MINIMIZING CACHE INTERRUPTIONS BY INHIBITING SNOOP CYCLES IF ACCESS IS TO AN EXCLUSIVE PAGE, and discloses a memory property tagging apparatus interfaced with one or more caches which are associated with one or more microprocessors of a multiprocessor system having shared memory and a bus network. The apparatus masks off any snoop cycles on the bus network if data corresponding to an address is exclusive to its associated microprocessor(s).
U.S. Pat. No. 5,410,654 issued Apr. 25, 1995 to Foster et al. for INTERFACE WITH ADDRESS DECODER FOR SELECTIVELY GENERATING FIRST AND SECOND ADDRESS AND CONTROL SIGNALS RESPECTIVELY IN RESPONSE TO RECEIVED ADDRESS AND CONTROL SIGNALS, and discloses interface circuitry for coupling to a microprocessor device. The interface circuitry includes circuitry for determining if a microprocessor-generated memory access is directed to a private memory, accessible only by the microprocessor device, or to a shared memory that is accessible by a plurality of microprocessor devices The interface circuitry includes a circuit for snooping the local bus.
U.S. Pat. No. 5,428,761 issued Jun. 27, 1995 to Herlihy et al. for SYSTEM FOR ACHIEVING ATOMIC NON-SEQUENTIAL MULTI-WORD OPERATIONS IN SHARED MEMORY, and discloses a computer system having a snoop mechanism for monitoring a bus to a shared memory to see if another processor references selected locations.
U.S. Pat. No. 5,502,828 issued Mar. 26, 1996 to Shah for REDUCING MEMORY ACCESS IN A MULTI-CACHE MULTIPROCESSING ENVIRONMENT WITH EACH CACHE MAPPED INTO DIFFERENT AREAS OF MAIN MEMORY TO AVOID CONTENTION, and discloses a cache control circuit for reducing accesses of main memory in a multiple cache multiprocessing system.
IBM Technical Disclosure Bulletin, vol. 32, No. Apr. 11, 1990, Pages 170-171, for SNOOP MECHANISM TO MONITOR COMPUTER BUS, discloses a mechanism for snooping the bus wherein the mechanism includes two registers used to specify the range of addresses to snoop, and wherein the address on the bus is fed into the control logic which is compared to see whether it is within the range.